Schematic of the chip/bump build-up cross-section.

What Are Through-Silicon Vias?

Faraday Technology Corporation-Flip-Chip Package

Advanced Flip Chip Packaging

State-Of-The-Art of Advanced Packaging

Chip Bonding - an overview

Solder Bump - an overview

PDF) Understanding and Improving Reliability for Wafer Level Chip

SEM image of a cross section of an unstressed 30 μm solder bump

a reliable wafer-level chip scale package (wlcsp) - AKRO Engineering

Zhuojie WU Research profile

Schematics of flip-chip bump and UBM structure

Multiple System and Heterogeneous Integration with TSV-Interposers

Weibull plots for TCoB fails based 1000 ohms and 0.1 ohms

A Brief Introduction of BGA Package Types